www.iterrac.com IT4131D x2, 2-to-4 ghz clock multiplier (preliminary information) this is a preliminary data sheet. see ?product status definitions? on web site or catalog for product development status. february 23, 2006 doc. 1371 rev 0 1 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 description features the IT4131D is a high-speed x2 clock multiplier using 1- m hbt gaas technology and employs an ecl topology to guarantee high-speed operation. it is an excellent ch oice for digital clock multiplication, instrumentation, and edge detection. digital clock mu ltiplication is implemented via xor operation between the input clock and an in ternal delayed replica. several embedded electrically-controlled phase delays are also employed. suitable regulation of the phase delay voltage controls allows duty cycle control on t he clock outputs. suitable power supply internal distribution provides the ability to disable the echo input which reduces power consumption. the IT4131D can also be stimulated via nrz data to perform edge detection. a dedicated temperature monitoring pin is also provided. ? clock input range: 2 to 4 ghz ? 900 mvpp typical single-ended output ? input sensitivity: si ngle-ended input >200 mv ? jitter rms <1 ps ? 50-ohm matched inputs and outputs (dc) device diagram v 0 -3.5 phase delay voltage control (fine duty cycle adjustment) vpf v 0 -3.5 phase delay voltage control (coarse duty cycle adjustment) vpc c 150 -65 storage temperature t stg c 125 -15 operating temperature range t a v 1.2 -1.2 data/clock input voltage level, low level v il v 1.2 -1.2 data/clock input voltage level, high level v ih v 0 -5.5 power supply voltage v ee units max. min. parameters/conditions symbol stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this document is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings ? compatible scfl i/o levels ? differential or single-ended i/o ? duty cycle control ? echo inputs available ? power consumption: 1.4 w
www.iterrac.com IT4131D x2, 2-to-4 ghz clock multiplier (preliminary information) this is a preliminary data sheet. see ?product status definitions? on web site or catalog for product development status. february 23, 2006 doc. 1371 rev 0 2 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 recommended operating conditions electrical characteristics v 0 dc input voltage (with dc-coupled input) vindc v -0.25 data/clock input voltage level, low level (single ended) vil v 0.25 data/clock input voltage level, high level (single ended) vih v -5 power supply voltage vee c 85 0 operating temperature range ta units max typ. min. parameters/conditions symbol w 1.6 1.4 1.2 power dissipation (4) pd ma 300 280 250 power supply current (4) ic ma 30 25 20 sub-harmonic suppression shs ps 1 0.9 0.7 rms jitter jrms ps 6 5 4 peak to peak jitter jpp ghz 4.0 1.4 input clock frequency fclk db 6 output return loss (up to 25 ghz) rlout db 15 input return loss (up to 25 ghz) rlin % 60 50 40 duty cycle control tdc v 0.8 -0.9 -1.0 data/clock output voltage level, low level (single ended) vol v 0 0 -0.1 data/clock output voltage level, high level (single ended) voh v vpmo n+0.4 vpmon-0.4 phase delay voltage control (fine duty cycle adjustment) vpf v vpmo n+0.4 vpmon-0.4 phase delay voltage control (coarse duty cycle adjustment) vpc v -2.4 -2.6 -2.8 internally generated reference voltage for 0 ps delay offset of the embedded phase delays (coarse and fine). (3) vpmon v 0.25 0 -0.75 dc input voltage (with dc-coupled input) (2) vindc v 0 -0.25 -1 data/clock input voltage level, low level (single ended) vil v 0.5 0.25 -0.5 data/clock input voltage level, high level (single ended) vih v -4.75 -5.0 -5.25 power supply voltage vee units max typ min parameters symbol 1. electrical characteristics at ambient temperature. 2. in case of single- ended inputs the unused pin has to be tied to vindc. in case of single- ended output, the unused pad must be terminated via 50 ohms to ground. 3. the pin vpmon can be left open or sensed with high- impedance load for temperature monitoring. 4. in case of echo inputs, an extra 60- ma (300-mw) at -5 v must be taken into account
www.iterrac.com IT4131D x2, 2-to-4 ghz clock multiplier (preliminary information) this is a preliminary data sheet. see ?product status definitions? on web site or catalog for product development status. february 23, 2006 doc. 1371 rev 0 3 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 eye diagram performance die measurement vee: -5.0 v clock input frequency: 1.5 ghz single-ended clock input: +/-250 mvpp die measurement vee: -5.0 v clock input frequency: 2.5 ghz single-ended clock input: +/-250 mvpp die measurement vee: -5.0 v clock input frequency: 3.0 ghz single-ended clock input: +/-250 mvpp die measurement vee: -5.0 v clock input frequency: 4.0 ghz single-ended clock input: +/-250 mvpp die measurement (edge detection application) vee: -5.0 v nrz input rate: 3.0 gb/s single-ended data input: +/-250 mvpp
www.iterrac.com IT4131D x2, 2-to-4 ghz clock multiplier (preliminary information) this is a preliminary data sheet. see ?product status definitions? on web site or catalog for product development status. february 23, 2006 doc. 1371 rev 0 4 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 recommended operational setup recommended mounting assembly bias conditions apply -5.0 v at vee1 apply -5.0 v at vee2 (if echo inputs must be provided) apply clock to the inputs vpc from -2.2 to -3.0 v for clock multiplication vpf from -2.2 to -3.0 v for duty cycle optimization (if necessary)
www.iterrac.com IT4131D x2, 2-to-4 ghz clock multiplier (preliminary information) this is a preliminary data sheet. see ?product status definitions? on web site or catalog for product development status. february 23, 2006 doc. 1371 rev 0 5 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 pad position and chip dimensions chip size: 1900 mm 10 mm x 2400 mm 10 mm chip thickness: 104 mm 3 mm pad size: 100 mm x 100 mm rf pad pitch: 150 mm
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